QL6250-6PT208M Ver la hoja de datos (PDF) - QuickLogic Corporation

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QL6250-6PT208M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Eclipse Family Data Sheet Rev. F

AC Characteristics at VCC = 2.5 V, TA = 25° C (K = 1.00)

The AC Specifications are provided from Table 13 to Table 21. Logic Cell diagrams and waveforms are

provided from Figure 16 to Figure 21.

Figure 16: Eclipse Logic Cell

Symbol

tPD

tSU

tHL

tCO

tCWHI

tCWLO

tSET

tRESET

tSW

tRW

Table 13: Logic Cells

Parameter

Value

Min.

Max.

Combinatorial Delay of the longest path: time taken by the combinatorial

circuit to output

0.205 ns 1.01 ns

Setup time: time the synchronous input of the flip flop must be stable before the

active clock edge

Hold time: time the synchronous input of the flip flop must be stable after the

active clock edge

Clock to out delay: the amount of time taken by the flip flop to output after the

active clock edge.

Clock High Time: required minimum time the clock stays high

Clock Low Time: required minimum time that the clock stays low

0.231 ns

0 ns

-

0.46 ns

0.46 ns

-

-

0.427 ns

-

-

Set Delay: time between when the flip flop is “set” (high) and when the output is

consequently “set” (high)

Reset Delay: time between when the flip flop is “reset” (low) and when the output

is consequently “reset” (low)

Set Width: time that the SET signal remains high/low

Reset Width: time that the RESET signal remains high/low

-

-

0.3 ns

0.3 ns

0.585 ns

0.658 ns

-

-

© 2007 QuickLogic Corporation

www.quicklogic.com

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