QL6250-6PT208M Ver la hoja de datos (PDF) - QuickLogic Corporation

Número de pieza

componentes Descripción

Fabricante

QL6250-6PT208M

Combining performance,density, and embedded RAM.

QuickLogic Corporation 

Figure 2: Eclipse Logic Cell

QS

A1

A2

A3

A4

A5

A6

OS

OP

B1

B2

C1

C2

MP

MS

D1

D2

E1

E2

NP

NS

F1

F2

F3

F4

F5

F6

PS

PP

QC

QR

Eclipse Family Data Sheet Rev. F

AZ

OZ

QZ

NZ

Q2Z

FZ

Table 3: Performance Standards

Function Description Slowest Speed Grade Fastest Speed Grade

Multiplexer

16:1

5 ns

2.8 ns

Parity Tree

Counter

FIFO

24

36

16 bit

32 bit

128 x 32

256 x 16

6 ns

6 ns

250 MHz

250 MHz

155 MHz

155 MHz

3.4 ns

3.4 ns

450 MHz

450 MHz

280 MHz

280 MHz

Clock to Out

System

clock

128 x 64

155 MHz

4.5 ns

200 MHz

280 MHz

2.5 ns

400 MHz

The second register has a two-to-one multiplexer controlling its input. The register can be loaded from the NZ

output or directly from a dedicated input.

NOTE: The input “PP” is not an “input” in the classical sense. It can only be tied high or low using default

links only and is used to select which path “NZ” or “PS” is used as an input to the register. All other inputs

can be connected not only to “tiehi” and “tielo” but to multiple routing channels as well.

The complete logic cell consists of 2 six-input AND gates, 4 two-input AND gates, 7 two-to-one multiplexers,

and 2 D flip-flop with asynchronous SET and RESET controls. The cell has a fan-in of 30 (including register

control lines) and fits a wide range of functions with up to 17 simultaneous inputs. It has 6 outputs;

4 combinatorial and 2 registered. The high logic capacity and fan-in of the logic cell accommodate many user

functions with a single level of logic delay while other architectures require two or more levels of delay.

© 2007 QuickLogic Corporation

www.quicklogic.com

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