AD7707 Ver la hoja de datos (PDF) - Analog Devices
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AD7707 Datasheet PDF : 40 Pages
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AD7707–SPECIFICATIONS
Parameter
B Version1
Units
Conditions/Comments
POWER REQUIREMENTS (Continued)
DVDD Current17
Power Supply Rejection 19
Normal Mode Power Dissipation17
Normal Mode Power Dissipation17
Standby (Power-Down) Current18
0.080
0.15
0.18
0.35
See Note 20
1.05
2.04
1.35
2.34
2.1
3.75
3.1
4.75
18
8
mA max
mA max
mA max
mA max
dB typ
mW max
mW max
mW max
mW max
mW max
mW max
mW max
mW max
µA max
µA max
Digital I/Ps = 0␣ V or DVDD. External MCLK IN
Typically 0.06␣ mA. DVDD = 3␣ V. fCLK IN = 1␣ MHz
Typically 0.13 mA. DVDD = 5␣ V. fCLK IN = 1␣ MHz
Typically 0.15␣ mA. DVDD = 3␣ V. fCLK IN = 2.4576␣ MHz
Typically 0.3␣ mA. DVDD = 5␣ V. fCLK IN = 2.4576␣ MHz
AVDD = DVDD = +3 V. Digital I/Ps = 0 V or DVDD.
External MCLK IN Excluding Dissipation in the AIN3
Attenuator
Typically 0.84 mW. BUF = 0. fCLK IN = 1␣ MHz, All Gains.
Typically 1.53 mW. BUF = 1. fCLK IN = 1␣ MHz, All Gains.
Typically 1.11 mW. BUF = 0. fCLK IN = 2.4576 MHz,
Gain = 1 to 4.
Typically 1.9 mW. BUF = 1. fCLK IN = 2.4576 MHz,
Gain = 1 to 4.
AVDD = DVDD = +5 V. Digital I/Ps = 0␣ V or DVDD.
External MCLKIN
Typically 1.75 mW. BUF = 0. fCLK IN = 1␣ MHz, All Gains.
Typically 2.9 mW. BUF = 1. fCLK IN = 1␣ MHz, All Gains.
Typically 2.6 mW. BUF = 0. fCLK IN = 2.4576 MHz.
Typically 3.75 mW. BUF = 1. fCLK IN = 2.4576 MHz.
External MCLK IN = 0 V or DVDD. Typically 9␣ µA.
AVDD = +5 V
External MCLK IN = 0 V or DVDD. Typically 4␣ µA.
AVDD = +3 V␣
NOTES
1 Temperature range as follows: B Version, –40°C to +85°C.
2 These numbers are established from characterization or design at initial product release.
3 A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables I and III for the low level input channels AIN1
and AIN2. This applies after calibration at the temperature of interest.
4 Recalibration at any temperature will remove these drift errors.
5 Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
6 Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
7 Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and full-scale error–bipolar zero error for
bipolar ranges.
8 Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.
9 Error is removed following a system calibration.
10 This common-mode voltage range is allowed provided that the input voltage on analog inputs does not go more positive than AVDD + 30 mV or go more negative
than AGND – 100␣ mV. Parts are functional with voltages down to AGND – 200 mV, but with increased leakage at high temperature.
11The analog input voltage range on AIN(+) is given here with respect to the voltage on LCOM on the low level input channels (AIN1 and AIN2) and is given with
respect to the HCOM input on the high level input channel AIN3. The absolute voltage on the low level analog inputs should not go more positive than AVDD +
100␣ mV, or go more negative than GND␣ – 100␣ mV for specified performance. Input voltages of AGND – 200 mV can be accommodated, but with increased leakage
at high temperature.
12 VREF = REF IN(+) – REF IN(–).
13These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
14 Sample tested at +25°C to ensure compliance.
15After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will
output all 0s.
16 These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30␣ mV or go more negative than AGND –
30␣ mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
17When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on
the crystal or resonator type (see Clocking and Oscillator Circuit section).
18If the external master clock continues to run in standby mode, the standby current increases to 150␣ µA typical at 5 V and 75 µA at 3 V. When using a crystal or
ceramic resonator across the MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation
depends on the crystal or resonator type (see Standby Mode section).
19Measured at dc and applies in the selected passband. PSRR at 50␣ Hz will exceed 120␣ dB with filter notches of 25 Hz or 50␣ Hz. PSRR at 60␣ Hz will exceed 120␣ dB
with filter notches of 20 Hz or 60␣ Hz.
20PSRR depends on both gain and AVDD.
Low Level Input Channels, AIN1 and AIN2
High Level Input Channel, AIN3
Gain
AVDD = 3 V
AVDD = 5 V
1 2 4 8–128
86 78 85 93
90 78 84 91
Specifications subject to change without notice.
Gain
1 2 4 8–128
AVDD = 3 V 68 60 67 75
AVDD = 5 V 72 60 66 73
–4–
REV. A
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