Pre-Production
REGISTER BIT
ADDRESS
LABEL
DEFAULT
WM8976
DESCRIPTION
0000 22.7us 182.4us 1.31ms
0001 45.4us 363us 2.62ms
0010 90.8us 726us 5.23ms
… (time doubles with every step)
1010
or
higher
23.2ms
186ms 1.34s
Table 17 ALC Control Registers
When the ALC is disabled, the input PGA remains at the last controlled value of the ALC. An input
gain update must be made by writing to the INPPGAVOLL/R register bits.
NORMAL MODE
In normal mode, the ALC will attempt to maintain a constant signal level by increasing or decreasing
the gain of the PGA. The following diagram shows an example of this.
Figure 11 ALC Normal Mode Operation
w
PP Rev 3.0 April 2006
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