WM8940CGEFL(2011) Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8940CGEFL Datasheet PDF : 91 Pages
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Production Data
WM8940
TABLE OF CONTENTS
DESCRIPTION....................................................................................................... 1
FEATURES ............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
BLOCK DIAGRAM ................................................................................................ 2
TABLE OF CONTENTS......................................................................................... 3
PIN CONFIGURATION .......................................................................................... 5
ORDERING INFORMATION.................................................................................. 5
PIN DESCRIPTION................................................................................................ 6
ABSOLUTE MAXIMUM RATINGS ........................................................................ 7
RECOMMENDED OPERATING CONDITIONS..................................................... 7
ELECTRICAL CHARACTERISTICS ..................................................................... 8
TERMINOLOGY ............................................................................................................ 10
AUDIO PATHS OVERVIEW ................................................................................ 11
POWER CONSUMPTION .................................................................................... 12
SIGNAL TIMING REQUIREMENTS .................................................................... 13
SYSTEM CLOCK TIMING ............................................................................................. 13
AUDIO INTERFACE TIMING – MASTER MODE .......................................................... 13
AUDIO INTERFACE TIMING – SLAVE MODE ............................................................. 14
CONTROL INTERFACE TIMING – 3-WIRE MODE ...................................................... 15
CONTROL INTERFACE TIMING – 2-WIRE MODE ...................................................... 16
DEVICE DESCRIPTION ...................................................................................... 17
INTRODUCTION ........................................................................................................... 17
INPUT SIGNAL PATH ................................................................................................... 18
ANALOGUE TO DIGITAL CONVERTER (ADC) ........................................................... 23
INPUT LIMITER / AUTOMATIC LEVEL CONTROL (ALC)............................................ 28
OUTPUT SIGNAL PATH ............................................................................................... 42
ANALOGUE OUTPUTS................................................................................................. 46
OUTPUT SWITCH ......................................................................................................... 50
DIGITAL AUDIO INTERFACES..................................................................................... 53
AUDIO SAMPLE RATES ............................................................................................... 57
MASTER CLOCK AND PHASE LOCKED LOOP (PLL) ................................................ 57
COMPANDING .............................................................................................................. 60
GENERAL PURPOSE INPUT/OUTPUT........................................................................ 62
CONTROL INTERFACE ................................................................................................ 63
3-WIRE SERIAL CONTROL MODE .............................................................................. 64
READBACK IN 3-WIRE MODE ..................................................................................... 64
2-WIRE SERIAL CONTROL MODE .............................................................................. 65
RESETTING THE CHIP ................................................................................................ 66
POWER SUPPLIES....................................................................................................... 66
POWER MANAGEMENT .............................................................................................. 68
POP MINIMISATION ..................................................................................................... 69
REGISTER MAP .................................................................................................. 70
REGISTER BITS BY ADDRESS ................................................................................... 71
DIGITAL FILTER CHARACTERISTICS .............................................................. 83
TERMINOLOGY ............................................................................................................ 83
DAC FILTER RESPONSES .......................................................................................... 84
ADC FILTER RESPONSES .......................................................................................... 84
HIGHPASS FILTER ....................................................................................................... 85
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PD, Rev 4.3, November 2011
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