WM8956
Production Data
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA=+25oC, Slave
Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
DACLRC propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
SYMBOL
tDL
tDST
tDHT
MIN
TYP
MAX
UNIT
10
ns
10
ns
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD1=SPKVDD2=3.3V, DGND=AGND=SPKGND1=SPKGND2=0V, TA=+25oC, Slave
Mode, fs=48kHz,
MCLK= 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
DACLRC set-up time to BCLK rising edge
DACLRC hold time from BCLK rising edge
DACDAT hold time from BCLK rising edge
DACDAT set-up time to BCLK rising edge
Note:
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
tDS
BCLK period should always be greater than or equal to MCLK period.
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
w
PD, November 2011, Rev 4.1
12