WM8956 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

Número de pieza

componentes Descripción

Fabricante

WM8956

Hi-Fi DAC with 1W Stereo Class D Speaker Drivers and Headphone Drivers

Wolfson Microelectronics plc 

WM8956

REGISTER BIT

ADDRESS

2

LABEL

DACMR

1

DACSLOPE

0

R7 (07h) 8

Audio

7

Interface

6

BCLKINV

MS

5

DLRSWAP

4

LRP

3:2 WL[1:0]

1:0 FORMAT[1:0]

R8 (08h) 8:6 DCLKDIV[2:0]

Clocking

(2)

5:4

DEFAULT

DESCRIPTION

Production Data

REFER TO

0

DAC Soft Mute Ramp Rate

Output Signal

0 = Fast ramp (fs/2, providing maximum delay of Path

10.7ms at fs=48k)

1 = Slow ramp (fs/32, providing maximum delay

of 171ms at fs=48k)

0

Selects DAC filter characteristics

0 = Normal mode

Output Signal

Path

1 = Sloping stopband

0

Reserved

0

Reserved

0

BCLK invert bit (for master and slave modes)

Audio Interface

0 = BCLK not inverted

Control

1 = BCLK inverted

0

Master / Slave Mode Control

0 = Enable slave mode

Audio Interface

Control

1 = Enable master mode

0

Left/Right DAC Channel Swap

Audio Interface

0 = Output left and right data as normal

Control

1 = Swap left and right DAC data in audio

interface

0

Right, left and I2S modes – LRCLK polarity

Audio Interface

0 = normal LRCLK polarity

Control

1 = invert LRCLK polarity

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising edge

after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising edge

after LRC rising edge (mode B)

10

Audio Data Word Length

00 = 16 bits

Audio Interface

Control

01 = 20 bits

10 = 24 bits

11 = 32 bits (see Note)

10

00 = Right justified

01 = Left justified

10 = I2S Format

Audio Interface

Control

11 = DSP Mode

111

Class D switching clock divider.

000 = Reserved

001 = SYSCLK / 2

010 = SYSCLK / 3

Class D Speaker

Outputs;

Clocking and

Sample Rates

011 = SYSCLK / 4

100 = SYSCLK / 6

101 = SYSCLK / 8

110 = SYSCLK / 12

111 = SYSCLK / 16

00

Reserved

w

PD, November 2011, Rev 4.1

62

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