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WM8956 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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WM8956 Datasheet PDF : 80 Pages
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Production Data
REGISTER BIT
ADDRESS
3:0
LABEL
BCLKDIV[3:0]
R9 (09h) 8:7
Audio
6
Interface
ALRCGPIO
DEFAULT
DESCRIPTION
0000
00
0
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 to 1111 = SYSCLK / 32
Reserved
GPIO1 Pin Function Select
0 = GPIO pin function disabled
1 = GPIO pin function enabled
5
WL8
4:3 DACCOMP[1:0]
2:0
R10 (0Ah) 8
Left DAC
Volume
7:0
DACVU
LDACVOL[7:0]
R11 (0Bh) 8
Right DAC
Volume
7:0
DACVU
RDACVOL[7:0]
R12 (0Ch) 8:0
R13 (0Dh) 8:0
0
8-Bit Word Length Select (Used with
companding)
0 = Off
1 = Device operates in 8-bit mode.
00
DAC companding
00 = off
01 = reserved
10 = µ-law
11 = A-law
000
Reserved
N/A
11111111
N/A
11111111
000000000
000000000
DAC Volume Update
Writing a 1 to this bit will cause left and right
DAC volumes to be updated (LDACVOL and
RDACVOL)
Left DAC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
DAC Volume Update
Writing a 1 to this bit will cause left and right
DAC volumes to be updated (LDACVOL and
RDACVOL)
Right DAC Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -127dB
0000 0010 = -126.5dB
... 0.5dB steps up to
1111 1111 = 0dB
Reserved
Reserved
WM8956
REFER TO
Clocking and
Sample Rates
General
Purpose Input /
Output;
Digital Audio
Interface
Audio Interface
Control
Audio Interface
Control
Output Signal
Path
Output Signal
Path
Output Signal
Path
Output Signal
Path
w
PD, November 2011, Rev 4.1
63

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