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Arria II Device Handbook

Unspecified 

July 2012

AIIGX51001-4.4

AIIGX51001-4.4

1. Overview for the Arria II Device Family

The Arria® II device family is designed specifically for ease-of-use. The

cost-optimized, 40-nm device family architecture features a low-power,

programmable logic engine and streamlined transceivers and I/Os. Common

interfaces, such as the Physical Interface for PCI Express® (PCIe®), Ethernet, and

DDR3 memory are easily implemented in your design with the Quartus® II software,

the SOPC Builder design software, and a broad library of hard and soft intellectual

property (IP) solutions from Altera. The Arria II device family makes designing for

applications requiring transceivers operating at up to 6.375 Gbps fast and easy.

This chapter contains the following sections:

■ “Arria II Device Feature” on page 1–1

■ “Arria II Device Architecture” on page 1–6

■ “Reference and Ordering Information” on page 1–14

Arria II Device Feature

The Arria II device features consist of the following highlights:

■ 40-nm, low-power FPGA engine

■ Adaptive logic module (ALM) offers the highest logic efficiency in the industry

■ Eight-input fracturable look-up table (LUT)

■ Memory logic array blocks (MLABs) for efficient implementation of small

FIFOs

■ High-performance digital signal processing (DSP) blocks up to 550 MHz

■ Configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision

multipliers as well as 18 x 36-bit high-precision multiplier

■ Hardcoded adders, subtractors, accumulators, and summation functions

■ Fully-integrated design flow with the MATLAB and DSP Builder software

from Altera

■ Maximum system bandwidth

■ Up to 24 full-duplex clock data recovery (CDR)-based transceivers supporting

rates between 600 Mbps and 6.375 Gbps

■ Dedicated circuitry to support physical layer functionality for popular serial

protocols, including PCIe Gen1 and PCIe Gen2, Gbps Ethernet, Serial

RapidIO® (SRIO), Common Public Radio Interface (CPRI), OBSAI,

SD/HD/3G/ASI Serial Digital Interface (SDI), XAUI and Reduced XAUI

(RXAUI), HiGig/HiGig+, SATA/Serial Attached SCSI (SAS), GPON,

SerialLite II, Fiber Channel, SONET/SDH, Interlaken, Serial Data Converter

(JESD204), and SFI-5.

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

Arria II Device Handbook Volume 1: Device Interfaces and Integration

July 2012

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