AD7564 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD7564

LC2MOS +3.3 V/+5 V, Low Power, Quad 12-Bit DAC

Analog Devices 

AD7564

Pin

Number

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Mnemonic

DGND

IOUT2C

VDD

IOUT1C

RFBC

VREFC

IOUT2D

IOUT1D

RFBD

VREFD

SDOUT

CLR

LDAC

FSIN

SDIN

CLKIN

A1

A0

VREFA

RFBA

IOUT1A

IOUT2A

VREFB

RFBB

IOUT1B

N/C

AGND

IOUT2B

PIN DESCRIPTIONS

Description

Digital Ground.

IOUT2 terminal for DAC C. This should normally connect to the signal ground of the system.

Positive power supply. This is +5 V ± 5%.

IOUT1 terminal for DAC C.

Feedback resistor for DAC C.

DAC C reference input.

IOUT2 terminal for DAC D. This should normally connect to the signal ground of the system.

IOUT1 terminal for DAC D.

Feedback resistor for DAC D.

DAC D reference input.

This shift register output allows multiple devices to be connected in a daisy chain configuration.

Asynchronous CLR input. When this input is taken low, all DAC latches are loaded with all 0s.

Asynchronous LDAC input. When this input is taken low, all DAC latches are simultaneously updated with the

contents of the input latches.

Level-triggered control input (active low). This is the frame synchronization signal for the input data. When FSIN

goes low, it enables the input shift register, and data is transferred on the falling edges of CLKIN. If the address

bits are valid, the 12-bit DAC data is transferred to the appropriate input latch on the sixteenth falling edge after

FSIN goes low.

Serial data input. The device accepts a 16-bit word. DB0 and DB1 are DAC select bits. DB2 and DB3 are device

address bits. DB4 to DB15 contain the 12-bit data to be loaded to the selected DAC.

Clock Input. Data is clocked into the input shift register on the falling edges of CLKIN. Add a pull-down resistor on

the clock line to avoid timing issues.

Device address pin. This input in association with A0 gives the device an address. If DB2 and DB3 of the serial

input stream do not correspond to this address, the data which follows is ignored and not loaded to any input

latch. However, it will appear at SDOUT irrespective of this.

Device address pin. This input in association with A1 gives the device an address.

DAC A reference input.

Feedback resistor for DAC A.

IOUT1 terminal for DAC A.

IOUT2 terminal for DAC A. This should normally connect to the signal ground of the system.

DAC B reference input.

Feedback resistor for DAC B.

IOUT1 terminal for DAC B.

No Connect pin.

This pin connects to the back gates of the current steering switches. It should be connected to the signal ground

of the system.

IOUT2 terminal for DAC B. This should normally connect to the signal ground of the system.

REV. B

–7–

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