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CY2071AFI Datasheet PDF : 9 Pages
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CY2071A
Operating Conditions[5]
Parameter
Description
VDD
Supply Voltage, 5.0V Operation
VDD
Supply Voltage, 3.3V Operation
TA
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
CL
Max. Load Capacitance per Output (5V Operation)
Max. Load Capacitance per Output (3.3V Operation)
fREF
External Reference Crystal
External Reference Clock[6, 7]
tPU
Power-up time for all VDDs to reach minimum specified voltage (power ramps
must be monotonic)
Min.
4.5
3.0
0
–40
–
–
10.0
1.0
0.05
Max.
5.5
3.6
70
85
25
15
25.0
30.0
50
Unit
V
V
°C
°C
pF
pF
MHz
MHz
ms
Electrical Characteristics, Commercial 5.0V: VDD = 5V ±10%, TA = 0°C to +70°C[8]
Parameter
Description
Conditions
Min.
VOH
HIGH-Level Output Voltage
IOH = –4.0 mA
2.4
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
–
VIH
HIGH-Level Input Voltage[9]
Except Crystal Pins
2.0
VIL
LOW-Level Output Voltage[9] Except Crystal Pins
–
IIH
Input HIGH Current
VIN = VDD – 0.5V
–
IIL
Input LOW Current
VIN = 0.5V
–
IOZ
Output Leakage Current
Three State Outputs
–
IDD
VDD Supply Current[10]
VDD = VDD max. 5V operation, CL = 25 pF
Typ.
–
–
–
–
–
–
–
40
Max. Unit
–
V
0.4 V
–
V
0.8 V
10 µA
150 µA
250 µA
60 mA
Electrical Characteristics, Commercial 3.3V: VDD = 3.3V ±10%, TA = 0°C to 70°C[8]
Parameter
Description
Conditions
Min.
VOH
HIGH-Level Output Voltage
IOH = –4.0 mA
2.4
VOL
LOW-Level Output Voltage
IOL = 4.0 mA
–
VIH
HIGH-Level Input Voltage[9]
Except Crystal Pins
2.0
VIL
LOW-Level Output Voltage[9] Except Crystal Pins
–
IIH
Input HIGH Current
VIN = VDD – 0.5V
–
IIL
Input LOW Current
VIN = 0.5V
–
IOZ
Output Leakage Current
Three State Outputs
–
IDD
VDD Supply Current[10]
VDD = VDD max. 3.3V operation, CL = 15 pF
–
Typ. Max. Unit
–
–
V
–
0.4 V
–
–
V
–
0.8 V
–
10 µA
–
150 µA
–
250 µA
24
40 mA
Notes:
5. Electrical parameters are guaranteed with these operating conditions. Values for 3.3V operation are shown in parentheses.
6. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
7. Please refer to application note “Crystal Oscillator Topics” for information on AC-coupling the external input reference clock.
8. See “CY2071A and CY2907 Clock Generators” Application Note for important customer clarification.
9. Xtal inputs have CMOS thresholds.
10. Load = max, typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula:
IDD(mA) = VDD*(6.25+(0.055*FREF) + (0.0017*CLOAD*(FCLKA+FCLKB+FCLKC))). CLOAD is specified in pF and F is specified in MHz.
Document #: 38-07139 Rev. *D
Page 3 of 9
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