ST8004 Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

ST8004

Smartcard interface

STMicroelectronics 

ST8004

6

Functional description

Functional description

Throughout this document it is assumed that the reader is familiar with iso7816 norm

terminology

6.1

Power supply

The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All

interface signals with the microcontroller are referenced to VDD; therefore be sure the supply

voltage of the microcontroller is also at VDD. All card contacts remain inactive during

powering up or powering down. The sequencer is not activated until VDD reaches Vth2

+Vhys(th2) or Vth3 + Vhys(th3) when VTHSEL = GND. When VDD falls below Vth2 or Vth3, an

automatic deactivation of the contacts is performed. To generate a 5 V ±5% VCC supply to

the card, an integrated voltage doubler is incorporated. This step-up converter should be

separately supplied by VDDP and PGND (from 4.5 to 6.5 V). In order to satisfy the

VI(RIPPLE)(P-P) specifications, VDDP should be from 4.75V to 5.25V. Due to large transient

currents, the 2x100 nF capacitors of the step-up converter should have an ESR of less than

100 mΩ, and be located as near as possible to the IC. The supply voltages VDD and VDDP

may be applied to the IC in any time sequence. To get the correct deactivation of the card

VDDP is allowed to turn-off only when VDD is below the undervoltage threshold. If a voltage

between 7 and 9 V is available within the application, this voltage may be tied to pin VUP,

thus blocking the step-up converter. In this case, VDDP must be tied to VDD and the capacitor

between pins S1 and S2 may be omitted.

6.2

Voltage supervisor (for VTHSEL = VDD or floating)

This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is

used internally for maintaining the IC in the inactive mode during powering up or powering

down of VDD (see Figure 3.). As long as VDD is less than Vth2 +Vhys(th2), the IC will remain

inactive whatever the levels on the command lines. This also lasts for the duration of tW after

VDD has reached a level higher than Vth2 +Vhys(th2).The system controller should not

attempt to start an activation sequence during this time. When VDD falls below Vth2, a

deactivation sequence of the contacts is performed.

6.3

Voltage supervisor (for VTHSEL = GND)

This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW) is

used internally for maintaining the IC in the inactive mode during powering up or powering

down of VDD (see Figure 6.). If VDD is less than Vth3 during a time, longer than ∆THFIL (max

150µs), the IC will remain inactive whatever the levels on the command lines. The IC remain

inactive also for the duration of tw after VDD has reached a level higher than Vth3. The

system controller should not attempt to start an activation sequence during this time. When

VDD falls below Vth3 during time more than ∆THFIL, a deactivation sequence of the contacts

is performed.

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