P3C1024L70TC Ver la hoja de datos (PDF) - Semiconductor Corporation

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P3C1024L70TC

ULTRA LOW POWER 128K x 8 CMOS STATIC RAM

Semiconductor Corporation 

P3C1024L

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6)

AC TEST CONDITIONS

Input Pulse Levels

Input Rise and Fall Times

Input Timing Reference Level

Output Timing Reference Level

Output Load

GND to 3.0V

3ns

1.5V

1.5V

See Fig. 1 and 2

TRUTH TABLE

Mode

Standby

Standby

Output

Disabled

Read

Write

CE

1

CE2

OE

WE

H XXX

X LXX

I/O

High Z

High Z

Power

Standby

Standby

L H H H High Z Active

LHLH

L HX L

D

OUT

DIN

Active

Active

Figure 1. Output Load

* including scope and test fixture.

Note:

Because of the high speed of the P3C1024L, care must be taken

when testing this device; an inadequate setup can cause a normal

functioning part to be rejected as faulty. Long high-inductance

leads that cause supply bounce must be avoided by bringing the VCC

and ground planes directly up to the contactor fingers. A 0.01 µF

high frequency capacitor is also required between VCC and ground.

Figure 2. Thevenin Equivalent

To avoid signal reflections, proper termination must be used; for

example, a 50Ω test environment should be terminated into a 50Ω

load with 1.75V (Thevenin Voltage) at the comparator input, and a

595Ω resistor must be used in series with DOUT to match 645Ω

(Thevenin Resistance).

Document # SRAM132 REV OR

Page 6 of 9

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