MACH111-12VI Ver la hoja de datos (PDF) - Lattice Semiconductor

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Fabricante

MACH111-12VI

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

100-PIN TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)

Top View

Block A

100-Pin TQFP

Block H

TDI

1

I5

2

I/O8

3

I/O9

4

I/O10

5

I/O11

6

I/O12

7

I/O13

8

I/O14

9

I/O15

10

I0/CLK0

11

VCC

12

GND

13

GND

14

I1/CLK1

15

I/O16

16

I/O17

17

I/O18

18

I/O19

19

I/O20

20

I/O21

21

I/O22

22

I/O23

23

NC

24

TCK

25

75

GND

74

TDO

73

NC

72

I/O55

71

I/O54

70

I/O53

69

I/O52

68

I/O51

67

I/O50

66

I/O49

65

I/O48

64

I4/CLK3

63

GND

62

VCC

61

I3/CLK2

60

I/O47

59

I/O46

58

I/O45

57

I/O44

56

I/O43

55

I/O42

54

I/O41

53

I/O40

52

I2

51

TMS

PIN DESIGNATIONS

CLK/I = Clock or Input

GND = Ground

I

= Input

I/O = Input/Output

VCC = Supply Voltage

Block D

Block E

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

46

MACH 1 & 2 Families

14051K-029

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