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DS3508

I2C, 8-Channel Gamma Buffer with EEPROM

Maxim Integrated 

I2C, 8-Channel Gamma Buffer with EEPROM

On power-up, the gamma data that is stored in each

channel’s EEPROM register is loaded into the corre-

sponding SRAM registers. The volatile CR register pow-

ers up as 00h, setting the device into mode 0.

DAC Description

The DACs are composed of a resistor string array and

a switching network per channel. A high-voltage array

with end points VHH and VHM controls outputs

GM1–GM4, and a low-voltage array with end points

VLM and VLL controls outputs GM5–GM8. The resistor

string arrays are composed of 255 identical resistors.

The switching networks can select any tap point

between adjacent resistors as well as either end point

(VHH/VHM or VLM/VLL pins). Table 1 shows the rela-

tionship between the 8-bit data and the DAC voltage.

SDA

I2C

8-BIT

SCL

SRAM

GMx

INTERFACE

DAC

A0

EEPROM

Figure 1. Single-Channel Block Diagram

VHH

VLL

CODE 0

RH1

CODE 1

RH2

CODE 2

RH3

RH253

CODE 253

RH254

CODE 254

RH255

VHM

VLM

CODE 255

Figure 2. DAC Block Diagram

RL1

RL2

RL3

RL253

RL254

RL255

CODE 0

CODE 1

CODE 2

CODE 253

CODE 254

CODE 255

8 _______________________________________________________________________________________

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