AA050ME01--T1 Ver la hoja de datos (PDF) - Unspecified
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AA050ME01--T1 Datasheet PDF : 26 Pages
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6. INTERFACE TIMING
(1) Timing Specifications
ITEM
SYMBOL MIN.
TYP.
MAX.
UNIT
Frequency
fCLK
--
33.5
45
MHz
DCLK
Period
Low Width
tCLK
22.2
29.9
--
tWCL
40%
--
--
ns
tCLK
High Width
tWCH
40%
--
--
tCLK
DATA(R,G,B), Set up time
DENA Hold time
tDS
4
--
--
ns
tDH
2
--
--
ns
Horizontal Active Time
tHA
800
800
800
tCLK
Horizontal Blank Time
tHB
164
256
348
tCLK
Horizontal Front Porch
tHFP
48
167
343
tCLK
Horizontal Back Porch
tHBP
5
89
116
tCLK
DENA Vertical Active Time
tVA
480
480
480
tH
Vertical Blank Time
tVB
35
45
55
tH
Vertical Front Porch
tVFP
2
12
22
tH
Vertical Back Porch
Frequency
Period
HD
Low Width
Set up time
tVBP
33
33
33
fH
--
31.5
35
tH
28.6
31.7
--
tWHL
1
--
--
Thst
6
--
--
tH
kHz
μs
tCLK
ns
Hold time
Thhd
6
--
--
ns
Frequency
Period
VD
Low Width
Set up time
fV
55
60
68
Hz
tV
14.7
16.7
18.2
ms
tWVL
1
--
--
tH
Tvst
6
--
--
ns
Hold time
Tvhd
6
--
--
ns
[Note]
1) DATA is latched at fall edge of DCLK in this specification.
2) Polarities of HD and VD are negative in this specification.
3) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
4) DCLK should appear during all invalid period, and HD should appear during invalid period of
frame cycle.
5) Please satisfy following condition.
tVBn = tVBn−1
MITSUBISHI
(10/25)
AA050ME01--T1_02_00
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