Parametric Test Circuits–AD5220
DUT
A
V+
W
B
V+ = VDD
1LSB = V+/128
VMS
OFFSET
GND
A DUT B
~ VIN
+5V
W
OP279
2.5V DC
VOUT
Figure 27. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Figure 31. Inverting Programmable Gain Test Circuit
NO CONNECT
DUT
A
W
B
IW
VMS
OFFSET
GND
~ VIN
W
+5V
OP279
A DUT B
2.5V
VOUT
Figure 28. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 32. Noninverting Programmable Gain Test Circuit
VMS2
DUT
A
W
B
IW = VDD/RNOMINAL
VW
VMS1
RW = [VMS1 – VMS2]/IW
␣␣
Figure 29.␣ Wiper Resistance Test Circuit
A
~ VIN
DUT
W
OFFSET
GND
B
2.5V
+15V
OP42
VOUT
–15V
Figure 33. Gain vs. Frequency Test Circuit
VA
~ VDD
V+
A
W
B
V+ = VDD ± 10%
( ) ⌬VMS
PSRR (dB) = 20 LOG –––––
⌬VDD
VMS
PSS (%/%) = –⌬–V–M––S–%–
⌬VDD%
Figure 30. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
DUT
W
B
RSW
=
0.1V
ISW
CODE = ØØH
ISW
0.1V
0 TO VDD
Figure 34. Incremental ON Resistance Test Circuit
REV. A
–7–