ST16C552CJ68TR-F Ver la hoja de datos (PDF) - Unspecified
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ST16C552CJ68TR-F Datasheet PDF : 39 Pages
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ST16C552/552A
same system design. The rate table is configured via the
DLL and DLM internal register functions. Customized
Baud Rates can be achieved by selecting the proper
divisor values for the MSB and LSB sections of baud rate
generator.
Programming the Baud Rate Generator Registers
DLM (MSB) and DLL (LSB) provides a user capability
for selecting the desired final baud rate. The example in
Table 5 below, shows the selectable baud rate table
available when using a 1.8432 MHz external clock
input.
Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432 MHz CLOCK):
Output
Baud Rate
MCR
Output
16 x Clock
Divisor
(Decimal)
User
16 x Clock
Divisor
(HEX)
DLM
Program
Value
(HEX)
50
2304
900
09
110
1047
417
04
150
768
300
03
300
384
180
01
600
192
C0
00
1200
96
60
00
2400
48
30
00
4800
24
18
00
7200
16
10
00
9600
12
0C
00
19.2k
6
06
00
38.4k
3
03
00
57.6k
2
02
00
115.2k
1
01
00
DLL
Program
Value
(HEX)
00
17
00
80
C0
60
30
18
10
0C
06
03
02
01
Rev. 3.40
12
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