CY7C1462AV25(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1462AV25
(Rev.:2004)

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Document History Page

Document Title: CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined

SRAM with NoBL™ Architecture

Document Number: 38-05354

Orig. of

REV. ECN No. Issue Date Change

Description of Change

** 254911 See ECN SYT New data sheet

Part number changed from previous revision (ew and old part number differ by the

letter "A”)

*A 303533 See ECN SYT Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA on

Page # 5

Changed the test condition from VDD = Min to VDD = Max for VOL in the Electrical

Characteristics table.

Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All Packages on

the Thermal Resistance Table

Changed IDD from 450, 400 & 350 mA to 435, 385 & 335 mA for 250, 200 and 167

Mhz respectively

Changed ISB1 from 190, 180 and 170 mA to 185 mA for 250, 200 and 167 Mhz

respectively

Changed ISB2 from 80 mA to 100 mA for all frequencies

Changed ISB3 from 180, 170 & 160 mA to 160 mA for 250, 200 and 167 Mhz respec-

tively.

Changed ISB4 from 100 mA to 110 mA for all frequencies

Changed CIN ,CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP

Package.

Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz Speed Bin

Added lead-free information for 100 TQFP, 165 FBGA and 209 BGA packages

Document #: 38-05354 Rev. *A

Page 27 of 27

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