Switching Characteristics, Industrial 3.3V (continued)
Parameter
Name
t9A
Clock Jitter[14]
t9B
Clock Jitter[14]
t9C
Clock Jitter[14]
t9D
Clock Jitter[14]
t10A
Lock Time for
CPLL
t10B
Lock Time for
UPLL and SPLL
Slew Limits
Description
Peak-to-peak period jitter (t9A max. – t9A min.),
% of clock period (fOUT < 4 MHz)
Peak-to-peak period jitter (t9B max. – t9B min.)
(4 MHz < fOUT < 16 MHz)
Peak-to-peak period jitter
(16 MHz < fOUT < 50 MHz)
Peak-to-peak period jitter
(fOUT > 50 MHz)
Lock Time from Power-up
Lock Time from Power-up
CPU PLL Slew Limits
CY2292I
CY2292FI
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t1
t2
OUTPUT
t3
t4
Output Three-State Timing[4]
OE
t5
t6
ALL
THREE-STATE
OUTPUTS
CLK Outputs Jitter and Skew
t9A
CLK
OUTPUT
t7
RELATED
CLK
Min.
20
20
Typ.
< 0.5
< 0.7
< 400
< 250
< 25
< 0.25
CY2292
Max.
1
1
500
350
50
1
66.6
60
Unit
%
ns
ps
ps
ms
ms
MHz
MHz
CPU Frequency Change
SELECT
OLD SELECT
Fold
CPU
NEW SELECT STABLE
t8 & t10
Fnew
Document #: 38-07449 Rev. *C
Page 8 of 11