SMJ4C1024-80JD Ver la hoja de datos (PDF) - Austin Semiconductor
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SMJ4C1024-80JD Datasheet PDF : 27 Pages
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RAS
CAS
A0 – A9
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
tw(RL)P
tw(RH)
td(RLCH)
td(RLCL)
tsu(CA)
th(RLCA)
td(RLCA)
th(RA)
tsu(RA)
Row
Column
tc(PM)
tw(CH)
tw(CL)
th(CA)
Column
td(CLRH)
td(CHRL)
Don’t Care
tsu(rd)
td(CAWL)
td(RLWL)
td(CLWL)
tsu(WCH)
tw(WL)
tsu(WRH)
W
Don’t Care
tsu(D)
th(D)
D
Don’t Care
Valid
Valid
Don’t Care
ta(R)
ta(C)
ta(CA)
ta(CP)
tdis(CH)
Q
See Note A
Valid
See Note A
Valid
Out
Out
NOTES: A. Output can go from high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
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