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MKL33Z128VLH4

Kinetis KL33 With Up To 256 KB Flash 48 MHz Cortex-M0+ Based Microcontroller

Freescale Semiconductor 

Pinouts and Packaging

5 Pinouts and Packaging

5.1 KL33 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

NOTE

VREFH can act as VREF_OUT when VREFV1 module is

enabled.

64 64

LQFP MAP

BGA

Pin Name

— E4 VDD

1 A1 PTE0

2 B1 PTE1

3 — VDD

4 C4 VSS

5 E1 PTE16

6 D1 PTE17

7 E2 PTE18

8 D2 PTE19

9 G1 PTE20

10 F1 PTE21

11 G2 PTE22

12 F2 PTE23

13 F4 VDDA

Default

ALT0

ALT1

ALT2

VDD

VDD

DISABLED LCD_P48

DISABLED LCD_P49

PTE0/

SPI1_MISO

CLKOUT32K

PTE1

SPI1_MOSI

VDD

VDD

VSS

VSS

ADC0_DP1/ LCD_P55/ PTE16

ADC0_SE1 ADC0_DP1/

ADC0_SE1

ADC0_DM1/ LCD_P56/ PTE17

ADC0_SE5a ADC0_DM1/

ADC0_SE5a

ADC0_DP2/ LCD_P57/ PTE18

ADC0_SE2 ADC0_DP2/

ADC0_SE2

ADC0_DM2/ LCD_P58/ PTE19

ADC0_SE6a ADC0_DM2/

ADC0_SE6a

ADC0_DP0/ LCD_P59/ PTE20

ADC0_SE0 ADC0_DP0/

ADC0_SE0

ADC0_DM0/ LCD_P60/ PTE21

ADC0_SE4a ADC0_DM0/

ADC0_SE4a

ADC0_DP3/ ADC0_DP3/ PTE22

ADC0_SE3 ADC0_SE3

ADC0_DM3/ ADC0_DM3/ PTE23

ADC0_SE7a ADC0_SE7a

VDDA

VDDA

SPI0_SS

SPI0_SCK

SPI0_MOSI

SPI0_MISO

ALT3

LPUART1_

TX

LPUART1_

RX

UART2_TX

UART2_RX

TPM1_CH0

TPM1_CH1

TPM2_CH0

TPM2_CH1

ALT4

RTC_

CLKOUT

TPM_

CLKIN0

TPM_

CLKIN1

I2C0_SDA

I2C0_SCL

LPUART0_

TX

LPUART0_

RX

UART2_TX

UART2_RX

ALT5

CMP0_OUT

SPI1_MISO

LPTMR0_

ALT3

SPI0_MISO

SPI0_MOSI

ALT6

I2C1_SDA

I2C1_SCL

FXI00_D0

FXIO0_D1

FXIO0_D2

FXIO0_D3

FXI00_D4

FXIO0_D5

FXIO0_D6

FXIO0_D7

ALT7

LCD_P48

LCD_P49

LCD_P55

LCD_P56

LCD_P57

LCD_P58

LCD_P59

LCD_P60

EzPort

52

Freescale Semiconductor, Inc.

Kinetis KL33 With Up To 256 KB Flash, Rev3, 08/2014.

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