CY7C1463AV33(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY7C1463AV33
(Rev.:2008)

36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

Truth Table

The truth table for CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 follows. [2, 3, 4, 5, 6, 7, 8]

Operation

Address

Used

CE1

CE2

CE3

ZZ ADV/LD WE BWX OE CEN CLK

DQ

Deselect Cycle

None H X X L

L

X X X L L->H Tri-State

Deselect Cycle

None X X H L

L

X X X L L->H Tri-State

Deselect Cycle

None X L X L

L

X X X L L->H Tri-State

Continue Deselect Cycle

None X X X L

H

X X X L L->H Tri-State

Read Cycle (Begin Burst)

External L H L L

L

H X L L L->H Data Out

(Q)

Read Cycle (Continue Burst)

Next

XXXL

H

X X L L L->H Data Out

(Q)

NOP/Dummy Read

(Begin Burst)

External L H L L

L

H X H L L->H Tri-State

Dummy Read (Continue Burst)

Next

XXXL

H

X X H L L->H Tri-State

Write Cycle (Begin Burst)

External L H L L

L

L L X L L->H Data In (D)

Write Cycle (Continue Burst)

Next

XXXL

H

X L X L L->H Data In (D)

NOP/Write Abort (Begin Burst)

None

LHL L

L

L H X L L->H Tri-State

Write Abort (Continue Burst)

Next

XXX

L

H

X H X L L->H Tri-State

Ignore Clock Edge (Stall)

Current X X X L

X

X X X H L->H

–

Sleep Mode

None X X X H

X

X X X X X Tri-State

Notes

2. X = “Don't Care.” H = logic HIGH, L = logic LOW. BWx = L signifies at least one byte write select is active, BWx = Valid signifies that the desired byte write selects

are asserted, see truth table for details.

3. Write is defined by BWX, and WE. See truth table for read or write.

4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.

5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE

is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.

Document #: 38-05356 Rev. *G

Page 11 of 32

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