CY7C1463AV33-133AXC(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1463AV33-133AXC
(Rev.:2008)

36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

The boundary scan register has a special bit located at bit #89

(for 165-FBGA package) or bit #138 (for 209-FBGA package).

When this scan cell, called the “extest output bus tri-state”, is

latched into the preload register during the “Update-DR” state in

the TAP controller, it directly controls the state of the output

(Q-bus) pins when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the

output bus. When LOW, this bit places the output bus into a

High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command and then shifting the desired bit into that cell,

TAP Timing

during the Shift-DR state. During Update-DR, the value loaded

into that shift register cell latches into the preload register. When

the EXTEST instruction is entered, this bit directly controls the

output Q-bus pins. Note that this bit is pre-set HIGH to enable

the output when the device is powered-up, and also when the

TAP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

1

2

3

4

5

6

Test Clock

(TCK)

Test Mode Select

(TMS)

t TH

tTL

tTMSS tTMSH

t CYC

t TDIS

t TDIH

Test Data-In

(TDI)

Test Data-Out

(TDO)

t TDOV

t TDOX

DON’T CARE

UNDEFINED

Document #: 38-05356 Rev. *G

Page 15 of 32

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