CY7C1463AV33-133AXC(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C1463AV33-133AXC
(Rev.:2008)

36 Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1461AV33

CY7C1463AV33, CY7C1465AV33

Identification Register Definitions

Instruction Field

CY7C1461AV33 CY7C1463AV33 CY7C1465AV33

(1M x 36)

(2M x 18)

(512K x 72)

Description

Revision Number (31:29)

Device Depth (28:24)[13]

000

01011

000

01011

000

01011

Describes the version number

Reserved for internal use

Architecture and Memory Type

(23:18)

001001

001001

001001

Defines memory type and

architecture

Bus Width and Density(17:12)

100111

010111

110111

Defines width and density

Cypress JEDEC ID Code (11:1)

00000110100 00000110100 00000110100 Allows unique identification of

SRAM vendor

ID Register Presence Indicator (0)

1

1

1

Indicates the presence of an ID

register

Scan Register Sizes

Register Name

Instruction

Bypass

ID

Boundary Scan Order (165-Ball FBGA Package)

Boundary Scan Order (209-Ball FBGA Package)

Bit Size (x36)

3

1

32

89

–

Bit Size (x18)

3

1

32

89

–

Bit Size (x72)

3

1

32

–

138

Identification Codes

Instruction

EXTEST

Code

000

IDCODE

001

SAMPLE Z

010

RESERVED

011

SAMPLE/PRELOAD

100

RESERVED

101

RESERVED

110

BYPASS

111

Description

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

Do Not Use: This instruction is reserved for future use.

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

Do Not Use: This instruction is reserved for future use.

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Note

13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05356 Rev. *G

Page 18 of 32

[+] Feedback

Share Link: