CY7C1441AV33-133AXC(2013) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1441AV33-133AXC Datasheet PDF : 34 Pages
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CY7C1441AV33
Truth Table
The truth table for CY7C1441AV33 follows. [1, 2, 3, 4, 5]
Cycle Description
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Sleep Mode, Power down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ
None
H X XL X
LX
X X L–H Tri-State
None
L L XL L
XX
X X L–H Tri-State
None
L X HL L
XX
X X L–H Tri-State
None
L L XL H
LX
X X L–H Tri-State
None
X X XL H
LX
X X L–H Tri-State
None
X X XH X
XX
X X X Tri-State
External
External
External
External
External
Next
Next
Next
L H LL L
L H LL L
L H LL H
L H LL H
L H LL H
X X XL H
X X XL H
H X XL X
XX
XX
LX
LX
LX
HL
HL
HL
X L L–H Q
X H L–H Tri-State
L X L–H D
H L L–H Q
H H L–H Tri-State
H L L–H Q
H H L–H Tri-State
H L L–H Q
Next
H X XL X
HL
H H L–H Tri-State
Next
X X XL H
HL
L X L–H D
Next
H X XL X
HL
L X L–H D
Current
X X XL H
HH
H
L L–H Q
Current
X X XL H
HH
H H L–H Tri-State
Current
H X XL X
HH
H
L L–H Q
Current
H X XL X
HH
H H L–H Tri-State
Current
X X XL H
HH
L X L–H D
Current
H X XL X
HH
L X L–H D
Notes
1. X = “Don't Care.†H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4.
The SRAM always initiates a read cycle when
the ADSP or with the assertion of ADSC. As a
ADSP
result,
is asserted,
OE must be
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clocks
a don't
after
care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05357 Rev. *K
Page 9 of 34
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