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74HC564N,652

Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

NXP Semiconductors. 

Philips Semiconductors

74HC564

Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

CP input

Dn input

VM

tsu

th

VM

tsu

th

Qn input

VM

001aab939

Fig 8.

The shaded areas indicate when the input is permitted to change for predictable output

performance.

VM = 0.5 × VI.

Waveforms showing the data set-up and hold times for the data input (Dn)

VI

PULSE

GENERATOR

VCC

VO

D.U.T.

RT

S1

RL =

1000 Ω

CL

mna232

VCC

open

GND

Test data is given in Table 9.

Definitions for test circuit:

RL = Load resistor.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse

generator.

Fig 9. Load circuitry for switching times

Table 9:

Supply

VCC

2.0 V

4.5 V

6.0 V

5.0 V

Test data

Input

VI

VCC

VCC

VCC

VCC

tr = tf

6 ns

6 ns

6 ns

6 ns

Load

CL

50 pF

50 pF

50 pF

15 pF

RL

1 kΩ

1 kΩ

1 kΩ

1 kΩ

S1

tPZL, tPLZ

VCC

VCC

VCC

VCC

tPZH, tPHZ

GND

GND

GND

GND

tPHL, tPLH

open

open

open

open

9397 750 13814

Product data sheet

Rev. 03 — 11 November 2004

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

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