NXP Semiconductors
74HC153-Q100; 74HCT153-Q100
Dual 4-input multiplexer
1E 1I3 1I2 1I1 1I0 S0 S1 2I3 2I2 2I1 2I0 2E
1Y
Fig 3. Logic diagram
5. Pinning information
5.1 Pinning
+&4
+&74
(
6
,
,
,
,
<
*1'
9&&
(
6
,
,
,
,
<
DDD
Fig 4. Pin configuration SO16
2Y
001aal845
+&4
+&74
(
6
O
O
O
O
<
*1'
9&&
(
6
O
O
O
O
<
DDD
Fig 5. Pin configuration TSSOP16
74HC_HCT153_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 November 2013
© NXP B.V. 2013. All rights reserved.
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