CY7C1383D-100AXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1383D-100AXC Datasheet PDF : 29 Pages
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CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
Test Mode Select
(TMS)
t TH
tTL
tTMSS tTMSH
t CYC
t TDIS
t TDIH
Test Data-In
(TDI)
Test Data-Out
(TDO)
DON’T CARE
t TDOV
t TDOX
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range [10, 11]
Parameter
Description
Min
Clock
tTCYC
TCK Clock Cycle Time
50
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
20
tTL
TCK Clock LOW time
20
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
0
Setup Times
tTMSS
TMS Setup to TCK Clock Rise
5
tTDIS
TDI Setup to TCK Clock Rise
5
tCS
Capture Setup to TCK Rise
5
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
5
tTDIH
TDI Hold after Clock Rise
5
tCH
Capture Hold after Clock Rise
5
Notes:
10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Max
20
10
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05544 Rev. *F
Page 13 of 29
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