S34ML01G204THB000 Ver la hoja de datos (PDF) - Spansion Inc.
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S34ML01G204THB000 Datasheet PDF : 79 Pages
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Data Sheet
As defined for Page
Program
Figure 3.1 Page Reprogram
Cycle Type
CMD ADDR ADDR ADDR ADDR ADDR
tADL
I/Ox
00h C1
C2
R1
R2
R3
SR[6]
A
Page N
Din
Din
Din
Din
CMD
D0
D1
...
Dn
10h
tWB
Cycle Type
CMD Dout
CMD ADDR ADDR ADDR ADDR ADDR CMD
A
tPROG
I/Ox
70h
E1
SR[6]
FAIL !
8Bh
C1
C2
R1
R2
R3
10h
tWB
tPROG
Page M
On the other hand, if the pattern bound for the target page is different from that of the previous page, data in
cycles can be issued before program confirm ‘10h’, as described in Figure 3.2.
Figure 3.2 Page Reprogram with Data Manipulation
As defined for Page
Program
Cycle Type
IOx
CMD ADDR ADDR ADDR ADDR ADDR
80h C1
C2
R1
R2
R3
tADL
SR[6]
A
Page N
Din
Din
Din
Din
CMD
D0
D1
...
Dn
10h
tWB
Cycle Type
I/Ox
CMD ADDR ADDR ADDR ADDR ADDR
8Bh
C1
C2
R1
R2
R3
tADL
SR[6]
Page M
Din
Din
Din
Din
CMD
D0
D1
...
Dn
10h
tWB
A
CMD Dout
tPROG
70h
E1
FAIL !
tPROG
The device supports Random Data Input within a page. The column address of next data, which will be
entered, may be changed to the address which follows the Random Data Input command (85h). Random
Data Input may be operated multiple times regardless of how many times it is done in a page.
The Program Confirm command (10h) initiates the re-programming process. The internal write state
controller automatically executes the algorithms and controls timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status
Register command may be issued to read the Status Register. The system controller can detect the
completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register.
Only the Read Status command and Reset command are valid when programming is in progress. When the
Page Program is complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only
errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read Status
command mode until another valid command is written to the command register.
September 5, 2014 S34ML01G2_04G2_10
Spansion® SLC NAND Flash Memory for Embedded
25
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