HT47C20L Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT47C20L Datasheet PDF : 45 Pages
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HT47C20L
Time Base
The time base offers a periodic time-out period to generate
a regular internal interrupt. Its time-out period ranges from
fS/212 to fS/215 selected by mask option. If time base
time-out occurs, the related interrupt request flag (TBF; bit
5 of INTC0) is set. But if the interrupt is enabled, and the
stack is not full, a subroutine call to location 08H occurs.
When the ²HALT² instruction is executed, the time base
still works and can wake up from halt mode. If the TBF is
set ²1² before entering the halt mode, the wake up function
will be disabled.
Real Time Clock - RTC
The real time clock is operated in the same manner as
the time base that is used to supply a regular internal in-
terrupt. Its time-out period ranges from fS/28 to fS/215 by
software programming. Writing data to RT2, RT1 and
RT0 (bits 2, 1, 0 of RTCC;09H) yields various time-out
periods. If a real time clock time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC0) is set. But if
the interrupt is enabled, and the stack is not full, a sub-
routine call to location 0CH occurs. The real time clock
time-out signal can also be applied as a clock source of
Timer/Event Counter A, so as to get a longer time-out
period.
RT2
RT1
RT0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
RTC Clock
Divided Factor
28
29
210
211
212
213
214
215
Power Down Operation - HALT
The halt mode is initialized by the ²HALT² instruction
and results in the following.
· The 32768Hz crystal oscillator will still work but the
system clock and T1 will turn off.
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT will be cleared and recount again.
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
· LCD driver is still running (by mask option).
· The time base and real time clock will still work.
The system can leave the halt mode by means of an ex-
ternal reset, an interrupt, an external falling edge signal
on port A or a WDT overflow. An external reset causes a
device initialization and the WDT overflow performs a
²warm reset². Examining the TO and PDF flags, the rea-
son for chip reset can be determined. The PDF flag is
cleared when system power-up or executing the ²CLR
WDT² instruction and is set when the ²HALT² instruction
is executed. The TO flag is set if the WDT time-out oc-
curs, and causes a wake-up that only resets the Program
Counter and SP, the others maintain their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by mask option. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If awakening from an interrupt, two sequences
may happen. If the related interrupt is disabled or the in-
terrupt is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt re-
sponse takes place.
If an interrupt request flag is set to ²1² before entering
the halt mode the wake-up function of the related inter-
rupt will be disabled.
fS /2 8
fS
D iv id e r
P r e s c a le r
M a s k O p tio n
T im e B a s e In te r r u p t
fS /2 1 2 ~ fS /2 1 5
Time Base
fS /2 8
fS
D iv id e r
P r e s c a le r
L C D D r iv e r fS /8
B uzzer
fS /2 2 ~ fS /2 9
R T2
R T1
R T0
8 to 1
M ux.
Real Time Clock
fS /2 8 ~ fS /2 1 5
R e a l T im e C lo c k In te r r u p t
Rev. 2.30
13
December 2, 2005
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