TDA9886HN/V5 Ver la hoja de datos (PDF) - NXP Semiconductors.
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TDA9886HN/V5
NXP Semiconductors.
TDA9886HN/V5 Datasheet PDF : 56 Pages
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NXP Semiconductors
TDA9885; TDA9886
I2C-bus controlled multistandard alignment-free IF-PLL demodulators
8. Functional description
Figure 1 shows the simplified block diagram of the device which comprises the following
functional blocks:
• VIF amplifier
• Tuner AGC and VIF AGC
• VIF-AGC detector
• Frequency Phase-Locked Loop (FPLL) detector
• VCO and divider
• AFC and digital acquisition help
• Video demodulator and amplifier
• Sound carrier trap
• SIF amplifier
• SIF-AGC detector
• Single reference QSS mixer
• AM demodulator
• FM demodulator and acquisition help
• Audio amplifier and mute time constant
• Internal voltage stabilizer
• I2C-bus transceiver and MAD
8.1 VIF amplifier
The VIF amplifier consists of three AC-coupled differential stages. Gain control is
performed by emitter degeneration and collector resistor variation. The total gain control
range is typically 66 dB. The differential input impedance is typically 2 kΩ in parallel with
3 pF.
8.2 Tuner AGC and VIF AGC
This block adapts the voltage, generated at the VIF-AGC detector, to the internal signal
processing at the VIF amplifier and performs the tuner AGC control current generation.
The onset of the tuner AGC control current generation can be set either via the I2C-bus
(see Table 12) or optionally by a potentiometer at pin TOP (in case that the I2C-bus
information cannot be stored, related to the device). The presence of a potentiometer is
automatically detected and the I2C-bus setting is disabled.
Furthermore, derived from the AGC detector voltage, a comparator is used to detect if the
corresponding VIF input voltage is higher than 200 µV. This information can be read out
via the I2C-bus (bit VIFLEV = 1).
TDA9885_TDA9886_3
Product data sheet
Rev. 03 — 16 December 2008
© NXP B.V. 2008. All rights reserved.
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