74LVT374 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LVT374 Datasheet PDF : 16 Pages
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NXP Semiconductors
74LVT374
3.3 V octal D-type flip-flop; 3-state
6. Functional description
6.1 Function table
Table 3. Function table [1]
Operating mode
Control
OE
Load and read register
L
Hold
L
Disable outputs
H
CP
NC
L or H
Input
Dn
l
h
X
X
Dn
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH clock transition;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition;
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition;
Z = high-impedance OFF-state;
NC = no change;
X = don’t care.
7. Limiting values
Internal register Output
Qn
L
L
H
H
NC
NC
NC
Z
Dn
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
VI
input voltage
VO
output voltage
IIK
input clamping current
IOK
output clamping current
output in OFF-state or HIGH-state
VI < 0 V
VO < 0 V
0.5
+4.6
V
[1] 0.5
+7.0
V
[1] 0.5
+7.0
V
-
50
mA
-
50
mA
IO
output current
output in LOW-state
output in HIGH-state
-
128
mA
-
64
mA
Tstg
storage temperature
Tj
junction temperature
Ptot
total power dissipation
Tamb = 40 C to +85 C
65
[2] -
[3] -
+150
C
150
C
500
mW
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] For SO20 packages: above 70 C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K.
74LVT374
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 14 September 2011
© NXP B.V. 2011. All rights reserved.
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