AD9694-500EBZ Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD9694-500EBZ Datasheet PDF : 101 Pages
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Data Sheet
AD9694
Addr
0x0564
0x056E
0x056F
0x0570
0x0571
Name
Bits
Pair map
[7:2]
output
channel
1
select
0
JESD204B [7:4]
map PLL
control
[3:0]
JESD204B 7
map PLL
STATUS
[6:4]
3
[2:0]
JESD204B [7:6]
map JTX
quick
configuration
[5:3]
[2:0]
JESD204B 7
map JTX Link
Control 1
6
Bit Name
Reserved
Reserved
Settings Description
Reserved.
Reserved.
Converter channel swap
control
0
1
JESD204B lane rate
control
0000
0001
0011
0101
Reserved
PLL lock status
0
1
Reserved
Reserved
Reserved
Quick Configuration L
0
1
Quick Configuration M
0
1
10
Quick Configuration F
0
1
10
11
Standby mode
0
1
Tail bit (t) PN
0
1
Normal channel ordering.
Channel swap enabled.
Lane rate = 6.75 Gbps to 13.5 Gbps.
Lane rate = 3.375 Gbps to 6.75 Gbps.
Lane rate = 13.5 Gbps to 15 Gbps.
Lane rate = 1.6875 Gbps to 3.375 Gbps.
Reserved.
Not locked.
Locked.
Reserved.
Reserved.
Reserved.
Number of lanes (L) = 20x0570[7:6].
L = 1.
L = 2.
Number of converters (M) = 20x0570[5:3].
M = 1.
M = 2.
M = 4.
Number of octets/frame (F) = 20x0570[2:0].
F = 1.
F = 2.
F = 4.
F = 8.
Standby mode forces zeros for all converter
samples.
Standby mode forces code group
synchronization (/K28.5/ characters).
Disable.
Enable.
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x1 R/W
0x1 R/W
0x1 R/W
0x0 R/W
0x0 R/W
Rev. 0 | Page 91 of 101
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