QL8050-8PS484C(2002) Ver la hoja de datos (PDF) - QuickLogic Corporation

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Fabricante

QL8050-8PS484C
(Rev.:2002)

Low Power FPGA Combining Performance, Density, and Embeded RAM

QuickLogic Corporation 

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There is one dedicated clock in the two larger devices of the Eclipse-II Family (QL8325 and

QL8250). This clock connects to the clock input of the LogicCell and I/O registers, and RAM

blocks through a hardwired connection and is multiplexed with the programmable clock input.

The dedicated clock provides a fast global network with low skew. Users have the ability to select

either the dedicated clock or the programmable clock ()LJXUH ).

Programmable Clock or

General Routing

Dedicated Clock

CLK

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Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and

EN inputs of I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant.

These buffers can be driven by the internal logic both as an I/O control or high drive. The

performance of these drives is presented in 7DEOH .

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I/O (far)

1.00 ns

1.14 ns

I/O (near)

0.63 ns

0.78 ns

Skew

0.37 ns

0.36 ns

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Eclipse-II devices are delivered with six types of routing resources as follows: short (sometimes

called segmented) wires, dual wires, quad wires, express wires, distributed networks, and default

wires. Short wires span the length of one logic cell, always in the vertical direction. Dual wires run

horizontally and span the length of two logic cells. Short and dual wires are predominantly used

for local connections. Default wires supply VCC and GND (Logic ‘1’ and Logic ‘0’) to each

column of logic cells.

Quad wires have passive link interconnect elements every fourth logic cell. As a result, these wires

are typically used to implement intermediate length or medium fan-out nets.

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