IRFD120, SiHFD120
Vishay Siliconix
VDS
Vary tp to obtain
required IAS
Rg
10 V
tp
L
D.U.T.
IAS
0.01 Ω
+
- VDD
Fig. 12a - Unclamped Inductive Test Circuit
VDS
VDS
tp
VDD
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
10 V
QGS
VG
QG
QGD
Charge
Fig. 13a - Basic Gate Charge Waveform
www.vishay.com
6
Current regulator
Same type as D.U.T.
12 V
50 kΩ
0.2 µF
0.3 µF
+
D.U.T. - VDS
VGS
3 mA
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
Document Number: 91128
S10-2462-Rev. C, 08-Nov-10