ICS83940D01L Ver la hoja de datos (PDF) - Integrated Device Technology
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ICS83940D01L Datasheet PDF : 15 Pages
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Low Skew, 1-to-18
LVPECL-TO-LVCMOS / LVTTL Fanout Buffer
83940-01
DATASHEET
GENERAL DESCRIPTION
The ICS83940-01 is a low skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL
Fanout Buffer. The ICS83940-01 has two selectable clock inputs. The
PCLK, nPCLK pair can accept LVPECL, CML or SSTL input levels. The
single ended clock input accepts LVCMOS or LVTTL input levels. The low
i m p e d a n c e LV C M O S / LV T T L o u t p u t s a r e d e s i g n e d
to drive 50Ω series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 18 to
36 by utilizing the ability of the outputs to drive two series
terminated lines.
The ICS83940-01 is character ized at full 3.3V, full 2.5V
and mixed 3.3V input and 2.5V output operat-
ing supply modes. Guaranteed output and part-to-part skew
characteristics make the ICS83940-01 ideal for those clock
distribution applications demanding well defined
performance and repeatability.
FEATURES
• Eighteen LVCMOS/LVTTL outputs, 23Ω typical output impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
• LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 250MHz
• Output skew: 85ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM
CLK_SEL
nPPCCLLKK
0
LVCMOS_CLK
1
PIN ASSIGNMENT
18
Q0:Q17
32 31 30 29 28 27 26 25
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
1
24
2
23
3
22
4 ICS83940-01 21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
Q6
Q7
Q8
VDDO
Q9
Q10
Q11
GND
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
83940-01 REVISION A NOVEMBER 4, 2014
1
©2014 Integrated Device Technology, Inc.
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