MPC9893 Ver la hoja de datos (PDF) - Integrated Device Technology
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MPC9893 Datasheet PDF : 14 Pages
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MPC9893 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
Table 1. Pin Configurations
Number
Name
CLK0, CLK1
Input
FB
Input
REF_SEL
Input
MAN/A
Input
ALARM_RST
Input
PLL_EN
Input
FSEL[0:3]
Input
OE/MR
Input
QA[0:5]
Output
QB[0:5]
Output
QFB
Output
ALARM0
Output
ALARM1
Output
CLK_IND
Output
GND
Supply
VCC_PLL
Supply
Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
VCC
Supply
VCC
Description
PLL reference clock inputs
PLL feedback signal input, connect directly to QFB output
Selects the primary reference clock
Selects automatic switch mode or manual reference clock selection
Reset of alarm flags and selected reference clock
Select PLL or static test mode
Clock frequency selection and configuration of clock divider modes
Output enable/disable and device reset
Bank A clock outputs
Bank B clock outputs
Clock feedback output. QFB must be connected to FB for correct operation
Indicates clock failure on CLK0
Indicates clock failure on CLK1
Indicates currently selected input reference clock
Negative power supply
Positive power supply for the PLL (analog power supply). It is recommended to use an
external RC filter for the analog power supply pin VCC_PLL. Please see the application
section for details.
Positive power supply for I/O and core
Table 2. Function Table
Control Default
0
1
Inputs
PLL_EN
0 PLL enabled. The input to output frequency relationship PLL bypassed and IDCS disabled. The VCO output is
is that according to Table 3 if the PLL is frequency
replaced by the reference clock signal fref. The MPC9893
locked.
is in manual mode.
MAN/A
1 Manual clock switch mode. IDCS disabled. Clock
Automatic clock switch mode. IDCS enabled. Clock failure
failure detection and output flags ALARM0, ALARM1, detection and output flags ALARM0, ALARM1, CLK_IND
CLK_IND are enabled.
are enabled. IDCS overrides REF_SEL on a clock failure.
IDCS operation requires PLL_EN = 0.
ALARM_RST
1 ALARM0, ALARM1 and CLK_IND flags are reset:
ALARM0, ALARM1 and CLK_IND active
ALARM0=H, ALARM1=H and CLK_IND=REF_SEL.
ALARM_RST is a one-shot function.
REF_SEL
0 Selects CLK0 as the primary clock source
Selects CLK1 as the secondary clock source
FSEL[0:3]
0000
See Table 3
OE/MR
0 Outputs enabled (active)
Outputs disabled (high impedance tristate), reset of data
generators and output dividers. The MPC9893 requires
reset at power-up and after any loss of PLL lock. Loss of
PLL lock may occur when the external feedback path is
interrupted. The length of the reset pulse should be greater
than two reference clock cycles (CLK0,1). OE/MR does not
tristate the QFB output.
Outputs (ALARM0, ALARM1, CLK_IND are valid if PLL is locked)
ALARM0
CLK0 failure
ALARM1
CLK_IND
CLK1 failure
CLK0 is the reference clock
CLK1 is the reference clock
MPC9893 REVISION 8 3/16/16
3
©2016 Integrated Device Technology, Inc.
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