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74ALVC16835PA Datasheet PDF : 6 Pages
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IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
1
NC
2
Y1
3
GND
4
Y2
5
Y3
6
VCC
7
Y4
8
Y5
9
Y6
10
GND
11
Y7
12
Y8
13
Y9
14
Y10
15
Y11
16
Y12
17
GND
18
Y13
19
Y14
20
Y15
21
VCC
22
Y16
23
Y17
24
GND
25
Y18
26
OE
27
LE
28
56
GND
55
NC
54
A1
53
GND
52
A2
51
A3
50
VCC
49
A4
48
A5
47
A6
46 GND
45
A7
44
A8
43
A9
42
A10
41
A11
40
A12
39 GND
38
A13
37
A14
36
A15
35
VCC
34
A16
33
A17
32 GND
31
A18
30 CLK
29 GND
TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
OE
CLK
LE
Ax
Yx
NC
Description
3-State Output Enable Inputs (Active LOW)
Register Input Clock
Latch Enable (Transparent LOW)
Data Inputs
3-State Outputs
No Internal Connection
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6
V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
±50
mA
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
ISS
VCC or GND
±100
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance VOUT = 0V
7
9
pF
COUT
I/O Port Capacitance VIN = 0V
7
9
pF
NOTE:
1. As applicable to the device type.
FUNCTION TABLE(1)
Inputs
Outputs
OE
LE
CLK
Ax
Yx
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
Y0(2)
L
L
L
X
Y0(3)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established,
provided that CLK is HIGH before LE went HIGH.
3. Output level before the indicated steady-state input conditions were established.
2
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