MAX4885 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
MAX4885 Datasheet PDF : 13 Pages
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Complete VGA 1:2 or 2:1 Multiplexer
RC
1MΩ
RD
1500Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
IP 100%
90%
AMPERES
36.8%
10%
0
0 tRL
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
TIME
tDL
CURRENT WAVEFORM
Figure 5. Human Body ESD Test Model
Figure 6. HBM Discharge Current Waveform
2:1 Multiplexer
In 2:1 mode, HSYNC and VSYNC buffers are disabled,
allowing bidirectional signaling. The DDC multiplexer
provides level shifting by clamping signals to a diode
drop less than VCL (see the Typical Operating Circuit).
Connect VCL to V+ to disable voltage clamping for
DDC signals.
Power-Supply Decoupling
Bypass each V+ pin and VCL to ground with a 0.1µF or
larger ceramic capacitor as close to the device as pos-
sible.
PC Board Layout
High-speed switches such as the MAX4885 require
proper PC board layout for optimum performance.
Ensure that impedance-controlled PC board traces for
high-speed signals are matched in length and as short
as possible. Connect the exposed pad to a solid
ground plane.
Chip Information
PROCESS: BiCMOS
CONNECT EXPOSED PAD TO GND
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