M48T212VSH Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

M48T212VSH

3.3V TIMEKEEPER® supervisor

STMicroelectronics 

M48T212V

Operation

Table 4. Chip enable control and bank select characteristics

M48T212V

Symbol

Parameter

–85

Unit

Min

Max

tEXPD

tAPD

EX to E1CON or E2CON (low or high)

A to E1CON or E2CON (low or high)

15

ns

15

ns

2.2

Note:

Read mode

The M48T212V executes a READ cycle whenever W (WRITE Enable) is high and E (Chip

Enable) is low. The unique address specified by the address inputs (A3-A0) defines which

one of the on-chip TIMEKEEPER® registers is to be accessed. When the address

presented to the M48T212V is in the range of 0h-Fh, one of the on-board TIMEKEEPER

registers is accessed and valid data will be available to the eight data output drivers within

tAVQV after the address input signal is stable, providing that the E and G access times are

also satisfied.If they are not, then data access must be measured from the latter occurring

signal (E or G) and the limiting parameter is either tELQV for E or tGLQV for G rather than the

address access time.

When EX input is low, an external SRAM location will be selected.

Care should be taken to avoid taking both E and EX low simultaneously to avoid bus

contention.

Figure 5. Read cycle timing: RTC control signal waveforms

ADDRESS

E

G

W

DQ7-DQ0

READ

tAVAV

READ

tAVAV

WRITE

tAVAV

tELQV

tAVQV

tAVWL

tWHAX

tELQX

tGLQV

tGLQX

tAXQX

DATA OUT

VALID

tWLWH

DATA OUT

VALID

tGHQZ

DATA IN

VALID

AI02640

Note:

EX is assumed high.

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