Q67006-A9146 Ver la hoja de datos (PDF) - Infineon Technologies

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Q67006-A9146

5-V Low-Drop Fixed Voltage Regulator

Infineon Technologies 

TLE 4268

Reset Timing

The power-on reset delay time is defined by the charging time of an external capacitor

CD which can be calculated as follows:

CD = (αtrd ⌠ ID,c)/αV

Definitions: CD = delay capacitor

αtrd = delay time

ID,c = charge current, typical 12 ←A

αV = VDU, typical 1.8 V

VDU = upper delay switching threshold at CD for reset delay time

The reset reaction time trr is the time it takes the voltage regulator to set the reset out

LOW after the output voltage has dropped below the reset threshold. It is typically 1 ←s

for delay capacitor of 47 nF. For other values for CD the reaction time can be estimated

using the following equation:

trr  20 s/F ⌠ CD

VΙ

VQ

VD

t rd

t rr

VRO

t

< t rr

V Q, rt

dV

dt

=

Ι D,c

CD

t

V DU

V DRL

t

Power-on-Reset

Thermal

Shutdown

CD

=

-----t--r--d---⌠-----I---D---Ι--c-----

VDU – VDRL

Voltage Dip

at Input

Undervoltage

Figure 5 Timing (Watchdog Disabled)

Secondary Overload

Spike at Output

t

AED03010

Data Sheet Rev. 1.2

10

2000-10-10

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