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MK10FN2M0AVMC15 Datasheet PDF : 75 Pages
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Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
J1
Description
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
0
0
0
Max.
10
20
40
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
1/J1
—
50
—
25
—
12.5
—
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
J6
Boundary scan input data hold time after TCLK rise
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
J11
TCLK low to TDO data valid
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
3
20
—
0
—
—
25
—
25
8
—
1.4
—
—
22.1
—
22.1
100
—
8
—
TCLK (input)
J2
J3
J3
J4
J4
Figure 5. Test clock input timing
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
K10 Sub-Family Data Sheet, Rev. 3, 6/2013.
24
Freescale Semiconductor, Inc.
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