JTS8388B-1V1B Ver la hoja de datos (PDF) - Unspecified
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JTS8388B-1V1B Datasheet PDF : 62 Pages
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TS8388B
Table 5-3. Electrical Specifications (Continued)
Parameter
Test
Value
Symbol
Level
Min
Typ
Max
Unit
50Ω differentially terminated
–
–
0.54
0.660
–
V
Output levels (assuming VPLUSD = 0V)
75Ω open transmission lines:
–
4
–
–
–
–
Logic “0” voltage
Logic “1” voltage
Output levels (assuming VPLUSD = 0V)
75Ω differentially terminated:
VOL
–
–
–1.62
–1.54
V
VOH
–
–0.88
–0.8
–
V
–
4
–
–
–
–
Logic “0” voltage
Logic “1” voltage
Output levels (assuming VPLUSD = 0V)
50Ω differentially terminated:
VOL
–
–
–1.41
–1.34
V
VOH
–
–1.07
–1
–
V
–
–
–
–
–
–
Logic “0” voltage
VOL
1, 2
–
–1.40
–1.32
V
6
–
–1.40
–1.25
V
Logic “1” voltage
VOH
1, 2
–1.16
–1.10
–
V
6
–1.25
–1.10
–
V
Differential Output Swing
DOS
4
270
300
–
mV
Output level drift with temperature
–
4
–
–
1.6
mV/°C
DC Accuracy (CBGA68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
TJ (typical) = 70°C
Differential nonlinearity
DNL-
1
–0.6
–0.4
–
lsb
Differential nonlinearity
DNL+
1
–
0.4
0.6
lsb
Integral nonlinearity
INL-
1
–1.2
–0.7
–
lsb
Integral nonlinearity
INL+
1
–
0.7
1.2
lsb
No missing codes
–
Guaranteed over specified temperature range
Gain
–
1, 2
90
98
110
%
Input offset voltage
–
1, 2
–26
–5
26
mV
Gain error drift
Offset error drift
–
4
100
125
150
ppm/°C
–
4
40
50
60
ppm/°C
DC Accuracy (CQFP68 package)
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format
TJ (typical) = 70°C.
Differential nonlinearity
1, 2
–0.5
–0.25
–
lsb
DNL-
6
–0.6
–0.35
–
lsb
Differential nonlinearity
1, 2
–
DNL+
6
–
0.3
0.6
lsb
0.4
0.7
lsb
Note
(6)
(6)
(6)
(2)(3)
(2)(3)
(3)
(2)(3)
6
0860F–BDC–12/09
e2v semiconductors SAS 2009
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