CXD3003R Ver la hoja de datos (PDF) - Sony Semiconductor

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CXD3003R

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony Semiconductor 

CXD3003R

TRK Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0)

TRK

Hold Reg

TRK

In Reg

Sin ROM

DFCT

2–1

K19

AGTON

K19

M0B

Z–1

∗

81H

2–7

K1A

M0C

Z–1

∗

7FH K1C

2–7

K1B

2–7

K1D

M0D

Z–1

∗

K1E 80H

2–7

K1F

2–7

K20

M0E

Z–1

TRK

AUTO Gain

M0F

K22

K23

K21

27

TRK PWM

TRK JMP

∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.

Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B

and K20 coefficients during quasi double accuracy to 0.

TRK Servo Gain up 1; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)

TRK

Hold Reg

DFCT

2–1

TRK

K19

In Reg

M0B

Z–1

∗

81H

2–7

K1A

M0C

Z–1

∗

∗

7FH 80H

2–7

K1B

2–7

K3C

M0E

Z–1

K3D

TRK

AUTO Gain

M0F

K3E

K23

27

TRK PWM

TRK JMP

∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.

Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0.

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