CL10K50VBC356-4 Ver la hoja de datos (PDF) - Clear Logic
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CL10K50VBC356-4 Datasheet PDF : 16 Pages
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LIBERATOR CL10K50V
AC Electrical Specifications cont.
External Bi-Directional Timing Parameters[5]
Symbol
Parameter
Speed: -1
Min Max
tINSUBIDIR
Setup for Bi-directional Pins with
Global Clock at Adjacent LE Registers
2.0
tINHBIDIR
Hold Time for Bi-directional Pins with
Global Glock at Adjacent LE Registers
0.0
tOUTCOBIDIR
Clock-to-output Delay for Bi-directional
Pins with Global Clock at IOE Register
2.0
5.9
tXZBIDIR
Synchronous IOE Output Buffer
Disable Delay
8.0
tZXBIDIR
Synchronous IOE Output Buffer
Disable Delay, Slow Slew Rate = off
8.0
Speed: -2
Min Max
2.8
0.0
2.0 7.8
9.8
9.8
Speed: -3
Min Max
3.5
0.0
2.0 9.5
11.8
11.8
Speed: -4
Min Max Unit
4.1
ns
0.0
ns
2.0 11.1 ns
14.3 ns
14.3 ns
10KA tbl 12A
AC Test Conditions
(A)
VCCIO
OUTPUT
35 pF
Includes jig
capacitance
703 Ω
8.06k Ω
(B)
VCCIO
703 Ω
OUTPUT
5 pF
Includes jig
capacitance
8.06k Ω
All Input Pulses
3.0V
90%
GND 10%
≤ 3ns
A: Test fixture set-up A is for general testing.
B: Test fixture set-up B is for high Z testing (tZX#).
90%
10%
≤ 3ns
10KA drw 02
Notes to Tables
1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for
periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V.
2. Device inputs may be driven before VCCINT and VCCIO are powered.
3. Typical values are at VCC of 3.3 volts and ambient temperature of 25 ºC.
4. Guaranteed but not tested. Characterized initially, and after any design changes
which may affect these parameters.
5. Internal timing delays are based on characterization, and cannot be explicitly
tested. Internal timing parameters should be used for performance estimation
only.
6. Use AC Test Conditions set-up B for these parameters.
Revision History
29 Feb. 2000:
01 Dec. 2000:
Created new document
Updated package availability and additional literature available
Page 14
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