CDC3205G-B1 Ver la hoja de datos (PDF) - Micronas
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CDC3205G-B1 Datasheet PDF : 6 Pages
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SHORT INFORMATION
CDC 32xxG
FVDD
UVDD
VDD
FVSS
UVSS
VSS
Data-,
52
address- and
control bus,
3.3V Reg.
2.5V Reg.
(Emu only)
EVDD
EVSS
21
WAIT
WAITH
VREFINT
VREF
AVDD
AVSS
BVDD
8
2.5V Reg.
ETM
(Emu only)
ARM7TDMI
CPU
DMA Logic
40 Input
Interrupt
Controller
24K SRAM
Reset/Alarm
Test
Watchdog
Clock
PLL/ERM
JTAG Test
and Debug
Interface
8
32
Wait Comp.
Memory
Controller
2
P06 Comp.
16
ROMless
or
512K Flash
RESETQ
TEST
TEST2
XTAL1
XTAL2
5
8
8
4
4
4
4
4
4
4
4
HVDD0
HVSS0
HVDD1
HVSS1
HVDD2
HVSS2
HVDD3
HVSS3
Bandgap Ref.
10Bit ADC
Bridge
8
Boot ROM
Patch Module
UART 0
UART 1
SPI 0
SPI 1
CAN 0
CAN 1
CAN 2
DIGITbus
I2C 0
I2C 1
LCD Control
Audio Module
Clock Out 0
Clock Out 1
Phase-Freq.-
Modulator
Stepper Motor
Control
8Bit PWM 0
8/16B PWM 1
8Bit PWM 2
8/16B PWM 3
8Bit PWM 4
8/16B PWM 5
8Bit PWM 6
8/16B PWM 7
8Bit PWM 8
8/16B PWM 9
8Bit PWM 10
8/16B PWM 11
16Bit Timer 0
8Bit Timer 1
8Bit Timer 2
8Bit Timer 3
8Bit Timer 4
16Bit CCC 0
CAPCOM 0
CAPCOM 1
CAPCOM 2
CAPCOM 3
16Bit CCC 1
CAPCOM 4
CAPCOM 5
7
8
4
4
3
4
6
UVDD
UVSS
Fig. 2: CDC 3205G-2 block diagram
Micronas ⋅ Oct/2000
5
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