AD22105ARZ-REEL Ver la hoja de datos (PDF) - Analog Devices
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AD22105ARZ-REEL Datasheet PDF : 11 Pages
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AD22105
APPLICATIONS INFORMATION
Figure 14 shows the typical application circuit.
+2.7V TO +7.0V
8
7
6
5
AD22105
RSET
OUT
1
2
3
4
Figure 14. Typical Application Circuit
ELECTROMAGNETIC INTERFERENCE (EMI)
SUPPRESSION
Noisy environments may couple electromagnetic energy into
the RSET node causing the AD22105 to falsely trip or untrip.
Noise sources, which typically come from fast rising edges, can
be coupled into the device capacitively. Furthermore, if the
output signal is close to the RSET pin, energy can couple from the
OUT pin to the RSET pin, potentially causing oscillation. Stray
capacitance can come from several places such as IC sockets,
multiconductor cables, and PCB traces. In some cases,
constructing a Faraday shield around the RSET pin can correct
this; for example, by using a shielded cable with the shield
grounded. However, for best performance, avoid cables and
directly solder the AD22105 to a PCB whenever possible. Figure 15
shows a sample PCB layout with low inter pin capacitance and
Faraday shielding. If stray capacitance is unavoidable, and
interference or oscillation occurs, connect a low impedance
capacitor from the RSET pin to the GND pin. This capacitor
must be considerably larger than the estimated stray capacitance.
Typically, several hundred picofarads corrects the problem.
Data Sheet
LEAKAGE AT THE RSET PIN
Leakage currents at the RSET pin, such as those generated from a
moist environment or PCB contamination, can have an adverse
effect on the programmed setpoint temperature of the AD22105.
Depending on the leakage source, leakage current can flow
into or out of the RSET pin. Consequently, the actual setpoint
temperature may be higher or lower than the intended setpoint
temperature by about 1°C for each 75 nA of leakage. With a 5 V
power supply, an isolation resistance of 100 MΩ creates 50 nA
of leakage current, resulting in a setpoint temperature error of
about 0.7°C (the RSET pin is near ground potential). Place a
guard ring around the RSET node to protect against leakage
from the power supply pin (as shown in Figure 15).
VS
C1
RSET
PIN 1
GND
OUT
Figure 15. Suggested PCB Layout
Rev. A | Page 10 of 11
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