HYB39S256400T-10 Ver la hoja de datos (PDF) - Infineon Technologies
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HYB39S256400T-10 Datasheet PDF : 56 Pages
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HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Column
Address Counter
Column Addresses
A0 - A8, AP,
BA0, BA1
Column
Address Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh
Counter
Row
Decoder
Memory
Array
Bank 0
8192 x
512 x
16 Bit
Row
Decoder
Memory
Array
Bank 1
8192 x
512 x
16 Bit
Row
Decoder
Memory
Array
Bank 2
8192 x
512 x
16 Bit
Row
Decoder
Memory
Array
Bank 3
8192 x
512 x
16 Bit
*) on SSTL versions only
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic & Timing Generator
CLK CKE CS RAS CAS WE DQMU DQML VREF *)
SPB03779
Block Diagram for 16 M × 16 SDRAM (13/9/2 addressing)
Semiconductor Group
6
1998-10-01
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