HYB39S256400T-10 Ver la hoja de datos (PDF) - Infineon Technologies
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HYB39S256400T-10 Datasheet PDF : 56 Pages
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HYB 39S256400/800/160T
256 MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Device
State
Bank Active
Idle3
Bank Precharge
Any
Precharge All
Any
Write
Active3
Write with Auto Precharge Active3
Read
Active3
Read with Auto Precharge Active3
Mode Register Set
Idle
No Operation
Any
Burst Stop
Active4
Device Deselect
Any
Auto Refresh
Idle
Self Refresh Entry
Idle
Self Refresh Exit
Idle
(Self
Refr.)
Clock Suspend Entry
Active
Power Down Entry
(Precharge or active
standby)
Idle
Active5
Clock Suspend Exit
Active
Power Down Exit
Any
(Power
Down)
Data Write/Output Enable Active
Data Write/Output Disable Active
CKE CKE DQM BS0 AP = Addr CS RAS CAS WE
n-1 n
BS1 A10
H
X
X
V
V
V
L
L
HH
H
X
X
V
L
X
L
L
H
L
H
X
X
X
H
X
L
L
H
L
H
X
X
V
L
V
L
H
L
L
H
X
X
V
H
V
L
H
L
L
H
X
X
V
L
V
L
H
L
H
H
X
X
V
H
V
L
H
L
H
H
X
X
V
V
V
L
L
L
L
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
X
L
H
H
L
H
X
X
X
X
X
H
X
X
X
H
H
X
X
X
X
L
L
L
H
H
L
X
X
X
X
L
L
L
H
H
X
X
X
L
H
X
X
X
X
L
H
H
X
H
L
X
X
X
X
X
X
X
X
H
X
X
X
H
L
X
X
X
X
L
H
H
X
L
H
X
X
X
X
X
X
X
X
H
X
X
X
L
H
X
X
X
X
L
H
H
L
H
X
L
X
X
X
X
X
X
X
H
X
H
X
X
X
X
X
X
X
Notes
1. V = Valid, X = Don’t Care, L = Low Level, H = High Level.
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BS0, BS1 signals.
4. Device state is Full Page Burst operation.
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode
cycle device is clock suspend mode.
Semiconductor Group
9
1998-10-01
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